Some integrated circuits have a clock or timing circuit that generates a clock signal that is synchronized with an input clock signal. For example, the timing circuit may generate a pulse when triggered by the rising edge of the input clock signal. In some of these integrated circuits, the timing circuit is used because the integrated circuit requires clock pulses with a pulse width that is different from the pulse width of the input clock signal. Further, the integrated circuit may have different operational modes that require different clock pulses. For example, in one mode the integrated circuit may require pulses triggered on the rising edges of a first clock signal, while in another mode the integrated circuit may require pulses triggered on the falling edges of a second clock signal. That is, the triggering edge of the input clock signal may be different depending on the integrated circuit's operational mode.
FIG. 1 is a circuit diagram illustrative of a conventional timing circuit 10. Timing circuit 10 includes an inverting delay circuit 11, a P-channel field effect transistor (PFET) 12, two N-channel FETs (NFETs) 13 and 14 and an inverting latch circuit 16. PFET 12 is connected to pull-up the voltage at a node N15, whereas NFETs 13 and 14 form a pull-down NFET stack also connected to node N15. The gate of NFET 13 is connected to an input signal CLK.sub.ir, whereas the gates of NFET 14 and PFET 12 are connected to receive input signal CLK.sub.ir via inverting delay circuit 11. Inverting delay circuit 11 provides a predetermined delay, designated herein as ".delta.". Latch circuit 16 has an input lead 15 connected to node N15 and generates an output signal CLK.sub.O at an output lead 17. Timing circuit 10 generates pulses synchronized with the rising edges of an input clock signal. In addition, the pulse width of the output pulses is determined by the duration of the delay provided by inverting delay circuit 11. Timing circuit 10 can generate signal CLK.sub.O with pulses having larger pulse widths than the input signal pulse widths, as described below.
FIG. 2 is a exemplary timing diagram illustrative of the operation of the timing circuit 10 (FIG. 1). Input signal CLK.sub.ir is represented by a waveform 21 in FIG. 2. In addition, the voltage at nodes N14 and N15 are represented by waveforms 22 and 23. Output signal CLK.sub.O is represented by a waveform 24. For clarity, the timing is illustrated in FIG. 2 with the propagation delays between circuit elements omitted.
Referring to FIGS. 1 and 2, timing circuit 10 operates as follows. Input signal CLK.sub.ir is received by inverting delay circuit 11, which outputs a signal at node N14 equivalent to an inverted and delayed version of input signal CLK.sub.ir. Thus, a rising edge 21.sub.1 of input signal CLK.sub.ir causes a falling edge 22.sub.1 in waveform 22 after a delay of about .delta.. Likewise, a falling edge 21.sub.2 in waveform 21 causes a rising edge 22.sub.2 in waveform 22 after a delay of about .delta.. As shown in FIG. 2, in this example the delay .delta. provided by inverting delay circuit 11 is greater than the pulse width of the pulses of input signal CLK.sub.ir.
Assuming initially that input signal CLK.sub.ir is at a logic low level while the voltage of nodes N14 and N15 are at logic high levels, output signal CLK.sub.O is at a logic high level, NFET 14 is turned on, and PFET 12 and NFET 13 are turned off. The logic levels of node N15 and output signal CLK.sub.O are maintained by inverting latch circuit 16. Thus, rising edge 21.sub.1 turns on NFET 13, which allows NFETs 13 and 14 to pull down the voltage at node N15 as indicated by falling edge 23.sub.1 of waveform 23. The falling edge 23.sub.1 in turn causes inverting latch circuit 16 to transition output signal CLK.sub.O to a logic high level, as indicated by rising edge 24.sub.1.
Subsequently, falling edge 21.sub.2 of waveform 21 occurs, thereby turning off NFET 13. However, because NFET 14 is already turned off, falling edge 21.sub.2 does not cause a transition in the voltage at node N15. Thus, output signal CLK.sub.O remains at a logic high level. However, when rising edge 21.sub.1 of input signal CLK.sub.ir propagates through delay circuit 11 after delay .delta. to cause falling edge 22.sub.1 in waveform 22, PFET 12 is turned on while NFET 14 is turned off. As a result, the voltage at node N15 is pulled up, causing rising edge 23.sub.2 in waveform 23, which in turn is inverted by inverting latch circuit 16 to cause a falling edge 24.sub.2 in output signal CLK.sub.O. Accordingly, output signal CLK.sub.O has a pulse with a pulse width equivalent to delay .delta., which was triggered by a rising edge of input signal CLK.sub.ir. After rising edge 22.sub.2 of waveform 22, the logic levels of waveforms 21-24 are returned to the previously described initial levels, awaiting for the next rising edge of input signal CLK.sub.ir to trigger another pulse in output signal CLK.sub.O with a pulse width of .delta..
FIG. 3 is a circuit diagram illustrative of a second conventional timing circuit 30, which is configured to be triggerable on either the rising edge or falling edge of an input signal. Timing circuit 30 incorporates timing circuit 10, with the addition of a two-input multiplexer 31 and a noninverting delay circuit 33. An input lead 35 of multiplexer 31 is connected to receive input signal CLK.sub.ir, whereas the other input lead 36 is connected to receive the output signal generated by noninverting delay circuit 33. Noninverting delay circuit 33 is connected to receive an input signal CLK.sub.if. In particular, timing circuit 30 is configured to generate output pulses that are triggered on the falling edges of input signal CLK.sub.if. Multiplexer 31 is connected to receive a mode signal M via a control lead 39 to selectively provide either input signal CLK.sub.ir or the output signal of noninverting delay circuit 33 to timing circuit 10. Mode signal M is generated by a mode control circuit (not shown).
Timing circuit 30 operates as follows. Mode signal M is used to configure timing circuit 30 into a first mode in which timing circuit 30 generates output pulses that are triggered by the rising edges of input signal CLK.sub.ir, or into a second mode in which timing circuit 30 generates output pulses that are triggered by the rising edges of input signal CLK.sub.if. When in the first mode, multiplexer 31 provides input signal CLK.sub.ir to timing circuit 10, which then generates output pulses as described above in conjunction with FIGS. 1 and 2. When in the second mode, multiplexer 31 provides a delayed version of input signal CLK.sub.if to timing circuit 10. The delay provided by noninverting delay circuit 33 is predetermined to delay input signal CLK.sub.if by a time equivalent to the pulse width of input signal CLK.sub.if so that, ideally, the rising edge of the signal generated by noninverting delay circuit 33 is coincident with the falling edge of input signal CLK.sub.if.
However, noninverting delay circuit 33 adds a relatively large amount of area to timing circuit 30. In addition, timing circuit 10 (and thus, timing circuit 30) does not operate properly when the pulse width of the input signals are relatively large compared to the cycle time (i.e., the input signal has a large duty cycle). In particular, problems occur when the duty cycle of the input signal is large enough so that the rising edge of a pulse occurs before the falling edge of the previous pulse has propagated tlrough delay circuit 11. More specifically, the first pulse will be generated properly, but subsequent pulses will be delayed from the rising edges of input signal CLK.sub.ir, as described below.
FIG. 4 is a timing diagram illustrative of the operation of timing circuit 10 when the input signal has such a duty cycle. Input signal CLK.sub.ir, the voltage at node N14, the voltage at node N15 and output signal CLK.sub.O are respectively represented by waveforms 41-44 in FIG. 4. Referring to FIGS. 3 and 4, assume initially that input signal CLK.sub.ir is at a logic low level while the voltage of nodes N14 and N15 are at logic high levels. As a result of these initial logic levels, output signal CLK.sub.O is at a logic low level, NFET 14 is turned on, and PFET 12 and NFET 13 are turned off. The logic levels of node N15 and output signal CLK.sub.O are maintained by inverting latch circuit 16.
Rising edge 41.sub.1 of waveform 41 turns on NFET 13, which allows NFETs 13 and 14 to pull down the voltage at node N15 as indicated by falling edge 43.sub.1 of waveform 43. The falling edge 43.sub.1 in turn causes inverting latch circuit 16 to transition output signal CLK.sub.O to a logic high level, as indicated by rising edge 44.sub.1.
Subsequently, due to the large duty cycle of input signal CLK.sub.ir, falling edge 42.sub.1 of waveform 42 occurs before the falling edge 41.sub.2 of waveform 41. Thus, PFET 12 is turned on while NFET 14 is turned off. As a result, the voltage at node N15 is pulled up, causing a rising edge 43.sub.2 in waveform 43, which in turn is inverted by inverting latch circuit 16 to cause a falling edge 44.sub.2 in output signal CLK.sub.O. Accordingly, the output pulse width of output signal CLK.sub.O is about equal to delay .delta..
Subsequently, falling edge 41.sub.2 occurs in input signal CLK.sub.ir, turning off NFET 13 and causing rising edge 42.sub.2 in waveform 42 after delay .delta.. In contrast to the first cycle of input signal CLK.sub.ir, because NFET 14 is already turned off by the logic low level of the voltage at node N14, there is no transition in the logic level of the voltage at node N15. Rising edge 41.sub.3 occurs, turning on NFET 14 before rising edge 42.sub.2 occurs in the voltage at node N14. However, because NFET 14 is off, turning on NFET 13 does not cause a transition in the voltage at node N15. Then when rising edge 42.sub.2 does occur, the logic high level of the voltage at node N14 turns on NFET 14 and turns off PFET 12, thereby allowing NFETs 13 and 14 to pull down the voltage at node N15. Thus, falling edge 43.sub.3 occurs in the voltage at node N15, which is propagated through inverting latch 16 to cause rising edge 44.sub.3 in output signal CLK.sub.O. As a result, the second pulse in output signal CLK.sub.O has a pulse width equal to the duration of the logic low period of input signal CLK.sub.ir. In addition, this second pulse is delayed relative to the rising edge of the second pulse of input signal CLK.sub.ir.
After the second pulse of output signal CLK.sub.O, the logic levels of waveforms 41-44 leading into the third pulse of input signal CLK.sub.ir, are returned to the previously described logic levels leading into the second pulse of input signal CLK.sub.ir. Accordingly, the next rising edge of input signal CLK.sub.ir results in the third output pulse being generated in the same way as the second output pulse (i.e., delayed).
Accordingly, there is a need for a timing circuit that can be triggered on the rising or falling edges of an input signal to generate output pulses having a pulse width that is substantially independent of the pulse width and duty cycle of the input signal.